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- Lu, Zhonghai, et al.
(författare)
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Feasibility analysis of messages for on-chip networks using wormhole routing
- 2005
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Ingår i: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2. - New York, New York, USA : IEEE conference proceedings. ; , s. 960-964
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Konferensbidrag (refereegranskat)abstract
- The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing properties. We present a novel feasibility analysis for real-time (RT) and non-realtime (NT) messages in wormhole-routed networks on chip. For RT messages, we formulate a contention tree that captures contentions in the network. For coexisting RT and NT messages, we propose a simple bandwidth partitioning method that allows us to analyze their feasibility independently.
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| 4. |
- Lu, Zhonghai, et al.
(författare)
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Refining synchronous communication onto network-on-chip best-effort services
- 2006
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Ingår i: Applications of Specification and Design Languages for SoCs. - DORDRECHT : Springer. - 1402049978 ; , s. 23-38
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Konferensbidrag (refereegranskat)abstract
- We present a novel approach to refine a system model specified with perfectly synchronous communication onto a network-on-chip (NoC) best-effort communication service. It is a top-down procedure with three steps, namely, channel refinement, process refinement, and communication mapping. In channel refinement, synchronous channels are replaced with stochastic channels abstracting the best-effort service. In process refinement, processes are refined in terms of interfaces and synchronization properties. Particularly, we use synchronizers to maintain local synchronization of processes and thus achieve synchronization consistency, which is a key requirement while mapping a synchronous model onto an asynchronous architecture. Within communication mapping, the refined processes and channels are mapped to an NoC architecture. Adopting the Nostrum NoC platform as target architecture, we use a digital equalizer as a tutorial example to illustrate the feasibility of our concepts.
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| 5. |
- Lu, Zhonghai, et al.
(författare)
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Towards performance-oriented pattern-based refinement of synchronous models onto NoC communication
- 2006
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Ingår i: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings. - 0769526098 ; , s. 37-44
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Konferensbidrag (refereegranskat)abstract
- We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four basic forms of NoC process interaction patterns at the process level, namely, producer-consumer, peers, client-server and multicast. We propose a three-step top-down refinement method: channel refinement, protocol refinement and channel mapping. For the producer-consumer pattern, we describe it in detail. In channel refinement, we deal with interfacing multiple clock domains and use a stochastic process to model channel delay and jitter In protocol refinement, we show how to refine communication towards application requirements such as reliability and throughput. In channel mapping, we discuss channel convergence and channel merge arising from channel overlapping. All the refinements have been conducted and validated as an integral design phase towards implementation in ForSyDe, a formal system-level design methodology based on a synchronous model of computation.
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| 6. |
- Lu, Zhonghai, et al.
(författare)
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Using synchronizers for refining synchronous communication onto Hardware/Software architectures
- 2007
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Ingår i: RSP 2007. - : IEEE Computer Society. - 9780769528342 ; , s. 143-149
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Konferensbidrag (refereegranskat)abstract
- We have presented a formal set of synchronization components called synchronizers for refining synchronous communication onto HW/SW codesign architectures. Such an architecture imposes asynchronous communication between HW-HW SW-SW and HW-SW components. The synchronizers enable local synchronization, thus satisfy the synchronization requirement of a typical IP core. In this paper we present their implementations in HW, SW and HW/SW as well as their application. To validate our concepts, we conduct a case study on a Nios FPGA that comprises a processor memory and custom logic. The final HW/SW implementation achieves equivalent performance to pure HW implementation. Our prototyping experience suggests that the synchronizers can be standardized as library modules and effectively separate the design of computation from that of communication.
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| 7. |
- Sander, Ingo, et al.
(författare)
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Development and application of design transformations in ForSyDe
- 2003
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Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 150:5, s. 313-320
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Tidskriftsartikel (refereegranskat)abstract
- The formal system design (ForSyDe) methodology has been developed for system level design. Starting with a formal specification model, which captures the functionality of the system at a high level of abstraction, it provides formal design transformation methods for a transparent refinement process of the specification model into an implementation model which is optimised for synthesis. The formal treatment of transformational design refinement is the central contribution of this article. Using the formal semantics of ForSyDe processes we introduce the term characteristic function to be able to define and classify transformations as either semantic preserving or design decision. We also illustrate how we can incorporate classical synthesis techniques that have traditionally been used with control/data-flow graphs as ForSyDe transformations. This approach avoids discontinuities as it moves design refinement into the domain of the specification model.
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